uniqc.visualization.circuit_render.layout module¶

Column layout engine for circuit rendering (shared by all output modes).

An ASAP (as-soon-as-possible) greedy layering assigns every op a column: each op lands on the first column where all of its lanes (qubit wires, cbit lanes, and for control-flow markers every lane) are free. Column widths are content-driven; the columns may then be folded into bands (rows of the final figure) according to a per-mode fold policy.

class uniqc.visualization.circuit_render.layout.FlowSpan(kind, cond, col_begin, col_end)[source]¶

Bases: object

A QIF/ENDQIF or QWHILE/ENDQWHILE bracket, in column coordinates.

col_begin¶

col_end¶

cond¶

kind¶

class uniqc.visualization.circuit_render.layout.Layout(ops, n_cols, col_widths, spans=<factory>, bands=<factory>)[source]¶

Bases: object

Laid-out circuit: ops carry col; bands fold columns into rows.

bands¶

col_widths¶

n_cols¶

ops¶

spans¶

uniqc.visualization.circuit_render.layout.estimate_text_width(text, font_size)[source]¶: Heuristic text width (px) — mirrors what the SVG browser render shows.

uniqc.visualization.circuit_render.layout.layout_circuit(draw, geom, param_mode, fold, mode='svg')[source]¶: Assign columns, compute column widths, and fold into bands.

uniqc.visualization.circuit_render.layout.resolve_fold(fold, mode, n_cols)[source]¶

Resolve the fold option to a concrete column count (0 = no fold).

fold="auto": for text output, fit the current terminal width; for graphical outputs (no fixed viewport) fold at 16 columns. fold=None is treated as "auto"; an int <= 0 disables folding.